Integrated circuits formed using complementary-metal-oxide-semiconductor (CMOS) processes for memory applications frequently use row and column decode circuits to address unique memory cells in the memory array. The output of the row decode circuit is often referred to as a wordline, and the output of the column decode circuit may be referred to as a bitline or column select line. Decoder size and complexity are principal design considerations, since it must fit the pitch of the memory cell. Additionally, the number of active control signals and address or factor lines required for each memory access may significantly affect power consumption of the integrated circuit due to the large number of decode circuits required for a typical memory array.
Trends toward faster access times and low voltage operation have led to the development of on-chip high voltage supplies for various circuit applications. This method eliminates the circuit delay and overvoltage penalty of conventional bootstrapping techniques. One particular application of the on-chip high voltage supply is in the row decoder where it is frequently necessary to elevate the wordline above the external supply potential. However, previous designs have been complicated by complex precharge schemes and level translation schemes which consume power and layout area. What is needed is a simple and compact row decoder for low power operation.